Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits

3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. In this paper, we investigate the interconnect distributions of 3-D circuits. We divide the 3-D interconnects into horizontal wires and vertical wires and derive their wire-length distributions, respectively. Based on the stochastic wire-length distributions, we calculate 3-D circuit interconnect delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters needed, and dramatically improve the performance. With 3-D structures, a circuit can work at a much higher clock rate (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay may limit the number of device layers that we can integrate.